Template:Intel processor roadmap: Difference between revisions
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And Netburst is not x86? And x86 was expanded to x86-64. The arch does not matter here. |
The talk page says not to mix CPU names and microarchitectures. The individual article pages say whether they’re a step or a new microarchitecture. This reflects what is written on each microarchitecture page. |
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|name=Intel processor roadmap |
|name=Intel processor roadmap |
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|title=Intel CPU core roadmaps from [[P6 (microarchitecture)|P6]] to Lunar Lake |
|title=Intel CPU core roadmaps from [[P6 (microarchitecture)|P6]] to Lunar Lake |
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|list1= |
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|list1=<noinclude>{{Cleanup section |
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| reason=When from ''Bonnell'' to ''Silvermont'' is [[Tick–tock model#Atom roadmap|just a Tick]] (die shrink) than ''Silvermont'' is part of ''Bonnell'' and not a unique microarchitecture? |
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| date=October 2019 |
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}}</noinclude> |
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<table class="wikitable" style="border:none; text-align:center;"> |
<table class="wikitable" style="border:none; text-align:center;"> |
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<tr> |
<tr> |
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<th rowspan="2">Feature size</th> |
<th rowspan="2">Feature size</th> |
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<td rowspan="38" style="background-color:white; border:none;"></td> |
<td rowspan="38" style="background-color:white; border:none;"></td> |
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<th colspan="2" style="background-color:#E6E6FF">[[ |
<th colspan="2" style="background-color:#E6E6FF">[[Pentium]]/[[Intel Core|Core]]</th> |
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<td colspan="6" rowspan="7" style="background-color:white; border:none;"></td> |
<td colspan="6" rowspan="7" style="background-color:white; border:none;"></td> |
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</tr> |
</tr> |
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<td colspan="2" rowspan="13"></td> |
<td colspan="2" rowspan="13"></td> |
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<th>[[600 nm process|600 nm]]</th> |
<th>[[600 nm process|600 nm]]</th> |
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<td rowspan=" |
<td rowspan="8"><b>[[P6 (microarchitecture)|P6]]</b></td> |
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<td>[[Pentium Pro]]<br>(133 MHz)</td> |
<td>[[Pentium Pro]]<br>(133 MHz)</td> |
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</tr> |
</tr> |
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</tr> |
</tr> |
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<tr> |
<tr> |
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<td rowspan="4">'''Pentium M'''</td> |
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<td>[[Banias (microprocessor)|Banias]]</td> |
<td>[[Banias (microprocessor)|Banias]]</td> |
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<td style="background-color:white; border:none;"></td> |
<td style="background-color:white; border:none;"></td> |
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<td>[[Haswell (microarchitecture)|Haswell]]</td> |
<td>[[Haswell (microarchitecture)|Haswell]]</td> |
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<td style="text-align:left; background-color:white; border:none;"></td> |
<td style="text-align:left; background-color:white; border:none;"></td> |
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<td colspan="6" style="text-align:left; background-color:white; border:none;"> |
<td colspan="6" style="text-align:left; background-color:white; border:none;">Fully integrated voltage regulator</td> |
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</tr> |
</tr> |
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<tr> |
<tr> |
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</tr> |
</tr> |
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<tr> |
<tr> |
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<td rowspan=" |
<td rowspan="3"><b>Goldmont</b></td> |
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<td rowspan="3">[[Goldmont]]</td> |
<td rowspan="3">[[Goldmont]]</td> |
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<td>[[Kaby Lake]]</td> |
<td>[[Kaby Lake]]</td> |
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</tr> |
</tr> |
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<tr> |
<tr> |
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<td rowspan="4"><b>Goldmont Plus</b></td> |
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<td rowspan="4">[[Goldmont Plus]]</td> |
<td rowspan="4">[[Goldmont Plus]]</td> |
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<td>[[Whiskey Lake]]</td> |
<td>[[Whiskey Lake]]</td> |
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<td colspan="6" style="background-color:white; text-align:left; border:none;">10 cores on mainstream desktop</td> |
<td colspan="6" style="background-color:white; text-align:left; border:none;">10 cores on mainstream desktop</td> |
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</tr> |
</tr> |
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<tr> |
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<td><b>'''Sunny Cove'''</b></td> |
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<td>[[Sunny_Cove_(microarchitecture)#Cypress_Cove|Cypress Cove]] ([[Rocket Lake]])</td> |
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<td style="text-align:left; background-color:white; border:none;"></td> |
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<td colspan="6" style="background-color:white; border:none; text-align:left;">Backported Sunny Cove microarchitecture for 14nm</td> |
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</tr> |
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<tr> |
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<td rowspan="3"><b>Tremont</b></td> |
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<td rowspan="3">[[Tremont (microarchitecture)|Tremont]]</td> |
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<th rowspan="3">[[10 nm process|10 nm]]</th> |
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<td>'''Skylake'''</td> |
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<td>Palm Cove ([[Cannon Lake (microarchitecture)|Cannon Lake]])</td> |
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<td style="text-align:left; background-color:white; border:none;"></td> |
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<td colspan="6" style="text-align:left; background-color:white; border:none;">Mobile-only</td> |
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</tr> |
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<tr> |
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<td rowspan="2">'''Sunny Cove'''</td> |
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<td>[[Sunny Cove]] ([[Ice Lake (microprocessor)|Ice Lake]])</td> |
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<td style="text-align:left; background-color:white; border:none;"></td> |
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<td colspan="6" style="background-color:white; text-align: left; border:none;">512 KB L2-cache/core</td> |
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</tr> |
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<tr> |
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<td>[[Willow Cove]] ([[Tiger Lake]])</td> |
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| ⚫ | |||
<td>[[Tiger Lake]]</td> |
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<td colspan="6" style="background-color:white; border:none; text-align:left;">[[Intel Xe|X<sup>e</sup>]] graphics engine</td> |
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<tr> |
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<td rowspan="2"><b>Gracemont</b></td> |
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<tr> |
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<td rowspan="2">[[Gracemont (microarchitecture)|Gracemont]]</td> |
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<th rowspan="2">[[7 nm process|Intel 7]]</th> |
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<td rowspan="2"><b>Golden Cove</b></td> |
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<td>[[Golden Cove]] ([[Alder Lake]])</td> |
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| ⚫ | |||
<td>[[Alder Lake]]</td> |
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<td colspan="6" style="background-color:white; border:none; text-align:left;">Hybrid, DDR5, PCIe 5.0</td> |
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<td colspan="6" style="background-color:white; border:none; text-align:left;">Hybrid, DDR5, PCIe 5.0</td> |
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<tr> |
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| ⚫ | |||
<tr> |
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<td>[[Raptor Lake]]</td> |
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<tr> |
<tr> |
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<td><b>Crestmont</b></td> |
<td><b>Crestmont</b></td> |
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Revision as of 12:02, 7 September 2023
Table format
This is a table with 13 columns × n rows, as derived from the graphic illustration worked up by the Commons Graphics Lab in a vertical format. The vertical format is used because the existing horizontal format is starting to require scrolling to display. This template version includes the complete P6 evolution (from its origin as the Pentium Pro microarchitecture) because of the added space afforded by the switch to vertical format.
However, updates to the existing template will require a bit more care, since tables are built row-by-row instead of column-by-column. <td rowspan=N> tags are used to expand cells beyond a single row, although that will require the editor to keep track of which cells and how many.
Columns are defined as:
- is the Atom family microarchitecture ("Atom TOCK")
- is the Atom processor codename ("Atom TICK")
- is a spacer column
- is the process/node range label (increasingly differing from actual feature size), and formatted as "<th rowspan="2">[[22 nm process|22 nm]]</th>", for instance.
- is a spacer column
- is the desktop/laptop family microarchitecture ("x86 TOCK")
- is the desktop/laptop processor codename ("x86 TICK")
- is a spacer column
- is the (single-core) NetBurst processor name. It is reserved to insert the NetBurst microarchitecture only, and is used solely to add NetBurst development in parallel with P6 development. Columns 9–13 are not anticipated to require any further updating unless Intel adds another parallel/stub branch of microarchitectures. Hence many of the row definitions end with a spacer such as <td colspan="5" style="background-color:white;border:none; text-align:left;"></td>.
- is a spacer column with arrows to show the derivation of Prescott
- is the (hyperthreading) NetBurst processor name.
- is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors
- is the (dual-core) NetBurst processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.
See also
- {{Intel technology}}
- {{Intel processor roadmap}}
- {{Intel graphics}}
- {{Intel software}}
- {{Intel processors}}
- {{Intel CPU sockets}}
- {{Intel controllers}}